The present invention relates to a memory device with features useful in, for example, the digital processing of moving pictures.
This type of processing is becoming increasingly necessary: television sets are making use of digital image-processing techniques; personal computers and workstations are being used to display video images; and moving pictures are being transferred between these different media, with attendant conversion between different formats.
Much digital image processing is performed on rectangular blocks of picture elements or pixels. Spatial and temporal filtering for noise rejection, effect processing, and format conversion are typical examples. Motion estimation for image compression is another example. When moving pictures are processed in real time, there is accordingly a need for very fast retrieval of blocks of pixels. For example, as each new pixel in a moving picture is received and stored, it may be necessary to read a block of pixels in which the new pixel occurs, and corresponding blocks of pixels from several preceding image frames or fields, all in the space of time before the next pixel is received.
Conventional dynamic random access memory (DRAM) is far too slow for this task, because every read or write access must be preceded by the time-consuming input of a new address.
Conventional dual-ported dynamic random-access memory, also known as video random-access memory (VRAM), can provide high-speed serial read access to an entire row of pixels, e.g. to all of the pixels in a horizontal scanning line on a screen, but this feature is not useful for access to rectangular blocks of pixels.
Synchronous dynamic random-access memory (SDRAM) and synchronous graphics random-access memory (SGRAM) permit burst access to smaller groups of pixels, but require separate address input for read access and write access, which is inconvenient when the arrival of each new pixel requires both types of access. SDRAM and SGRAM also fail to support some of the burst lengths most often required in digital filtering.
Moreover, none of these memories can be easily cascaded to provide access to pixel blocks in several frames or fields.
The inadequacies of existing types of random-access memory have often forced system designers to use first-in-first-out (FIFO) memory for storing fields and frames, and provide an application-specific integrated circuit (ASIC) with line memories for use in accessing rectangular blocks of pixels. An ASIC with twenty-one line memories, each a static random-access memory (SRAM) storing one thousand twenty-four eight-bit words, has been used in digital television receivers, for example. SRAM memory cells are large, however, so the line memories take up much space in the ASIC, limiting the amount of actual image-processing circuitry that can be accommodated. The SRAM line memories also consume much current, because they are operated as shift registers, and their presence increases the cost of the ASIC.
Further details will be given below.